The present invention relates to a semiconductor device with an SOI (silicon on insulator) structure having an ESD (electro static discharge) protection element for protecting an inner circuit from a large current exceeding a rated current due to static charge or lightening. The present invention also relates to a method of producing the semiconductor device.
In a conventional semiconductor device with an SOI structure having an ESD protection element, an insulating layer is formed on a bulk layer. A semiconductor layer is formed on the insulating layer as a semiconductor layer of a laminated substrate of the SOI structure. An N well layer and a P well layer are formed in the semiconductor layer to form an SCR (silicon controlled rectifier) element as the ESD protection element for protecting an inner circuit from an influence of static charge (refer to Patent Reference 1).
Patent Reference 1: Japanese Patent Publication (Kokai) No. 2003-318265
In general, the SCR element formed on a silicon substrate has a structure shown in FIG. 11. In the SCR element 1 shown in FIG. 11, a P type silicon substrate 2 is formed of a silicon layer with a p type impurity such as boron and aluminum diffused uniformly. An N well layer 3 is formed in the silicon substrate 2 by partially diffusing an N type impurity such as phosphorous and arsenic. An N+ area 4a with the N type impurity diffused at a higher concentration and a P+ area 5a with the P type impurity diffused at a concentration higher than that of the N type impurity of the N well layer 3 are formed on a surface of the N well layer 3. The N+ area 4a and P+ area 5a are connected to an anode 6. An N area 4c with the N type impurity partially diffused and a P area 5c with the P impurity partially diffused are formed in the silicon substrate 2 adjacent to the N well layer 3, and are connected to a cathode 7.
In an operation of the SCR element 1, when a voltage is applied between the anode 6 and the cathode 7, the N+ area 4a and the P+ area 5a formed on the N well layer 3 have a same potential. Accordingly, an opposite voltage is applied to the N+ area 4a, so that electron holes do not flow through a P-N connection between the N well layer 3 and the P+ area 5a. When the voltage reaches a breakdown voltage Vt1 as shown in FIG. 12, a suppression balance of the P-N connection between the N well layer 3 and the P+ area 5a is broken down. Accordingly, a current rapidly flows between the anode 6 and the cathode 7 through the P+ area 5a, the N well layer 3, the P type semiconductor substrate 2, and the N+ area 4c. As a result, an on resistance Ron decreases, and a current flows with a small hold voltage Vh, thereby reducing power consumption of the SCR element 1 and heat generation thereof. Accordingly, it is necessary to provide the N well layer 3 in the SCR element 1 to perform the thyristor operation.
Recently, an operational speed and a packaging density of a semiconductor have been increased. As a result, a size of a semiconductor element has been reduced, thereby reducing a gate length of an MOS (metal oxide semiconductor) element. Accordingly, a semiconductor having an SOI structure has become a main stream. In the semiconductor having an SOI structure, a thin silicon layer is formed on an insulating layer formed on a bulk layer as a semiconductor layer, thereby reducing a short channel effect due to a high packaging density.
In the conventional technology described above, the SCR element is formed on the semiconductor layer as the ESD protection element. Accordingly, when the semiconductor layer is formed of a thin silicon layer, it is difficult to form the well layer necessary for the SCR element. As a result, the SCR element does not have sufficient function as the ESD protection element. When the semiconductor layer has a large thickness to form the well layer, it is difficult to reduce the short channel effect and obtain the high packaging density.
In view of the problems described above, an object of the present invention is to provide a method of producing a semiconductor device, in which it is possible to form an ESD protection element operating effectively even when a semiconductor with an SOI structure has a thin semiconductor layer.
Further objects and advantages of the invention will be apparent from the following description of the invention.